A flash memory device is a non-volatile semiconductor memory device, which retains its memory contents even if it is powered off. Flash memory devices offer fast read access time and better shock resistance compared to hard disks. As a result, flash memory devices are popular for applications, such as storage on battery-powered devices, and are extensively used in consumer electronic products.
In certain flash memory devices, one bit of information is stored in each memory cell. More recently, flash memory devices have been developed to store more than one bit per cell. Such devices are often referred to as “multi-level cell” devices. Such multi-level cell devices, such as Nitride Read Only Memory (NROM) devices, include a nitride storage material.
A single NROM cell typically includes a nitride trapping layer overlying a channel region provided between source and drain regions. The NROM cell can be programmed to store two physically separated bits in the nitride trapping layer, in the form of a concentration of charge near the source region and another concentration of charge near the drain region. Programming of the NROM cell can be performed by Channel Hot Electron (CHE) injection, which generates hot electrons in the channel region. Some of these hot electrons gain enough energy to become trapped in the nitride trapping layer. By interchanging the biases applied to the source and drain terminals, the charge is trapped either in a portion of the nitride trapping layer near the source region, near the drain region, or both.
Accordingly, for example, if no charge is stored in the memory cell, the threshold voltage of the memory cell has a minimal value corresponding to a combination of bits 0 and 0. If charge is stored in the nitride trapping layer near the source region, but not near the drain region, the threshold voltage has a different value corresponding to a combination of bits 1 and 0, for example. The threshold voltage has yet another value if charge is stored near the drain region but not near the source region. In that case, the threshold voltage corresponds to a combination of bits 0 and 1. Lastly, if charge is stored near both the source and the drain region, the threshold voltage is at its highest, and corresponds to a combination of bits 1 and 1. Thus, four distinct combination of bits 00, 01, 10 and 11 can be stored, and each combination has a corresponding threshold voltage. During a read operation, current flowing through the memory cell will vary depending upon the threshold voltage of the cell. Typically, such current will have four different values, each corresponding to a different threshold voltage. Accordingly, by sensing such current, the particular bit combination stored in the cell can be determined.
The total available charge range or the threshold voltage range may be referred to as memory operation window. In other words, memory operation window is defined by the difference between program level and erase level. A large memory operation window is desirable because good level separation between states is needed for multi-level cell operation
The performance of two-bit memory cells, however, is often degraded by the so-called “second bit effect” in which localized charges in the trapping layer interact with each other. For example, during a reverse read operation, a read bias is applied to the drain terminal and the charge stored near the source region (i.e., a “first bit”) is sensed. The charge near the drain region (i.e., the “second bit”), however, creates a potential barrier for reading the first bit near the source region. This barrier may be overcome by applying a bias with a suitable magnitude, using the drain-induced barrier lowering (DIBL) effect to suppress the effect of the second bit near the drain region and allow the sensing of the storage status of the first bit. However, when the second bit near the drain region is programmed to a high threshold voltage state and the first bit near the source region is programmed to a low threshold voltage state, the second bit raises this barrier substantially. Therefore, as the threshold voltage associated with the second bit increases, the read bias for the first bit becomes insufficient to overcome the potential barrier created by the second bit. As a result, the threshold voltage associated with the first bit is raised as a result of the increasing threshold voltage of the second bit, thereby reducing the memory operation window.
The second bit effect decreases the memory operation window for 2-bit/cell operation and/or multi-level cell (MLC) operation. Therefore, there is a need for methods and devices for suppressing the second bit effect in memory devices.